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CS22210 Data Sheet
Wireless PCI/USB Controller
1
Description
The Cirrus Logic CS22210 Wireless Network Controller enables high speed, 11 Mbps digital wireless data connectivity for wireless data connectivity for PCI, mobile, embedded systems and other cost sensitive applications. The CS22210 is a highly integrated single-chip PCI / USB solution for wireless networks supporting video, audio, voice, and data traffic. The programmable controller executes Cirrus Logic's WhitecapTM2 networking protocol that provides Wi-FiTM (802.11b) compliance as well as multimedia and quality of service (QoS) support. The device includes several high performance components including an ARM7TDMI RISC processor core, a Forward Error Correction (FEC) codec and a wireless Radio MAC supporting up to11 Mbps throughput. The CS22210 is designed to support both a standard PCI 2.1 or PCI 2.2 compliant interface or USB 1.1 compliant device interface making it an ideal choice for cost effective standalone and embedded high-speed wireless networking products. The CS22210 utilizes state-of-the-art 0.18um CMOS process and is housed in a 208 MQFP package designed to provide integrated low cost IEEE 802.11 standard compliant system solutions. The core is powered at 1.8 V to reduce overall power consumption. In addition, the CS22210 supports various power management modes for host, MAC, baseband, and radio interfaces.
Figure 1. Example System Block Diagram PCI or USB Host
Networking Data 802.11b compatible 2.4 GHz Digital Radio PHY Transceiver 11 Mbps Wireless Baseband I/F System Memory SDRAM (Up to 4MB) SRAM (Up to 256KB) Boot ROM/Flash (Up to 1MB)
CS22210 Wireless Network Controller
2.4 GHz Direct Sequence Spread Spectrum
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Features
Embedded ARM Core and System Support Logic * High performance ARM7TDMI RISC processor core at 77MHz * 4KB integrated, one-way set associative, unified, write through cache * Individual interrupt for each functional block * Two 23-bit programmable (periodic or one-shot) general purpose timers * 8 Dword (32-bits) memory write and read buffers for high system performance * Abort cycle detection and reporting for debugging * ARM performance monitoring function for system fine-tuning * Programmable performance improvement logic based on system configuration * Flexible independent DMA engines for PCI, USB and digital radio functional units Enhanced Memory Controller Unit * Programmable memory controller unit supporting SDRAM /async SRAM/boot ROM interface * 16-bit data bus with 12-bit address supporting up to 4MB at up to 103MHz SDRAM * 8-bit data bus with addressing support up to 1MB of boot ROM/Flash * Programmable SDRAM timing and size parameters such as CAS latencies and number of banks columns and rows FEC codec * High performance Reed-Solomon coding for error correction (255:239 block coding) * Reduces symbol error probability of a typical 10e-3 error rate environment to 10e-9 * Programmable rate FEC engine to optimize channel efficiency * Low latency, fully pipelined hardware encoding and decoding. Support byte wise single cycle throughput up to 77MHz, with a sustain rate of 77MBps. * Double buffering (64 Dword read/write buffer) to enhance system performance * On the fly configuration of encoder and decoder Digital Wireless Radio MAC * Standard interface to 802.11b radio baseband transceiver * 11Mbps data rate * 32 Dword transmit/receive FIFO * Supports clear channel assessment (CCA) Power Management * Host (PCI or USB) ACPI compliant * Remote USB host wakeup * Supports variable rate radio transmit, receive and standby radio power modes through two DACs Clock and PLL Interface * Single 44MHz crystal oscillator reference clock for PCI version; 48MHz reference clock required in USB option * Internal PLL to generate internal and on board clocks
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PCI Controller Interface * 33MHz 5V/3.3V PCI 2.1 and PCI 2.2 compliant master/target 32-bit data interface * ARM communication with PCI controller through simple mailbox scheme * Generic PCI controller programming interface * Flexible configuration programming via EEPROM USB Controller Interface * 12 Mbps USB 1.1 compliant device * Supports 1 to 16 endpoints; endpoints can be bulk, isochronous or interrupt * Variable endpoint buffer depths providing maximum flexibility for endpoint configurations * Flexible configuration programming via EEPROM or firmware download * Remote host wakeup Chip Processing and Packaging * 208 MQFP package and 0.18 um state of the art CMOS process * 1.8 V core for low power consumption; 3.3V I/O and 5V tolerant
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
Use of this product in any manner that complies with the MPEG-2 video standard as defined in ISO documents IS 13818-1 (including annexes C, D, F, J, and K), IS 13818-2 (including annexes A, B, C, and D, but excluding scalable extensions), and IS 13818-4 (only as it is needed to clarify IS 13818-2) is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C. 250 Steele Street, Suite 300, Denver, Colorado 80296.
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Functional Description
Figure 2. Block Diagram of Major Functional Units
PCI Interface USB or PCI Host Interface USB Interface DMA CTRL
DMA
System Memory System Memory Memory/Boot ROM Controller Arbiter
DMA
Read/Write Buffer ARM 7TDMI Dual Radio MAC W/ DMA Ctrl 4KB Cache
JTAG/Test Interface
12MHz or 33 MHz
Comm Buffer
Interrupt controller
Radio Interface
Timer (2)
44MHz
77MHz System Control Bus
Sleep Timer
FEC CODEC
Misc. Config.
Clock/PLL
48MHz / 44 MHz
Crystal or Oscillator
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3.1
Embedded ARM Core and System Support Logic
The processing elements of the CS22210 include the ARM7TDMI core and its associated system control logic. The ARM processor and system controller consist of a memory management unit, 4-KB write through cache controller, 20 IRQ and 4 FIRQ interrupt controller, and 2 general purpose timers. The ARM processor and integrated system support logic provide the necessary execution engine to support a real time multi-tasking operating system, the network protocol stack, and firmware services. In addition, system performance monitor logic is included to aid in system performance fine-tuning (e.g. cache hit, CPI numbers). Memory Management Unit ARM instructions and data are fetched from system memory a cache-line (4/8 - Dwords /Programmable) at a time when caching is turned on. During a cache line fill, critical word data, i.e., the access that caused the miss, is forwarded to the ARM and also written into the data RAM cache. The non-critical words in the line fetched following the critical word are then written to the cache on a Dword basis, as they become available. Memory writes are posted to dual 4-Dwords (32-bit) memory write posting buffers. Write posts use the sequential addressing feature on the memory bus. With dual buffering an out of sequence write will post to one write buffer while the other buffer is flushed to memory. There is one 8Dword Read Buffer in the MEM block. The buffer is used for both cacheable and non-cacheable memory space. Interrupt Controller The interrupt controller provides two interrupt channels to the ARM processor. One interrupt channel is presented to the ARM on its nFIQ, and the other channel is presented on its nIRQ pin. These are referred to as the FIQ channel and the IRQ channel. Both channels operate in identical but independent fashion. The FIQ channel has a higher priority on the ARM processor than the IRQ channel. The interrupt controller includes a CONTROL register for each logical interrupt in the ARM complex. The CONTROL register serves the following main purposes: * * * Provides the mapping between the EXT_INT inputs (physical interrupts) and the logical interrupt Selects the particular type of signaling expected on the EXT_INT inputs: level, edge, active level high/low etc. Enables or disable a logical interrupt
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3.2
Digital Wireless Radio Interface
The CS22210 digital radio MAC I/F supports multiple radio baseband and RF interfaces. baseband registers can be programmed during the configuration time using the control interface. The MAC also provides the capability of programming the signal, service length on per packet basis without ARM intervention. This significantly improves performance of the system. The port and the
There are three primary digital interface ports for the CS22210 that are used for configuration and during normal operation. These ports are: * The Control Port, which is used to configure, set power consumption modes, write and/or read the status of the radio base band registers. * The TX Port, which is used to output the data that needs to be transmitted from the network processor. * The RX Port, which is used to input the received demodulated data to the network processor.
3.3
FEC Codec
The FEC codec performs Reed-Solomon code encoding to protect the data before it is transmitted to a noisy channel. It is a similar code as employed by digital broadcast industry, such as ITU-T J.83 for DVB. The RS(255, 239) code implemented by the SWG2710 can reduce error probability to 1/10e-9 in a typical 1/10e-3 error rate environment. The encoder/decoder can be programmed to vary the coding block length (N) and correctable error (t) to optimize the tradeoff between channel utilization and data protection. The range of N is currently set to be from 50 to 255, and the t is 8. The symbol size is fixed at 8 bits. Coding parameters can be set real time, allowing maximum flexibility for the system to adjust the FEC setting, such as block size, in order to optimize channel efficiency. The encoder also has a very low latency of two cycles. Both the encoder and decoder are fully pipelined in structure to achieve single cycle throughput. The FEC can be disabled in firmware.
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3.4
Programmable Memory Controller
The CS22210 incorporates a general purpose memory controller that supports a SDRAM/async SRAM memory and FLASH memory interface. In the RAM configuration, the system memory interface supports up to 16-Mbyte of 16-bit SDRAM running at a frequency up to 103 MHz single-state access cycles or 256KB of 16 bit async SRAM. The memory controller provides programming of SDRAM parameters such as CAS latency, refresh rate etc; these registers are located in miscellaneous configuration registers. When there are no pending memory requests from any internal requester, the CS22210 will keep Clock Enable (CKE) signal low to cause the SDRAM to stay in power down mode. Once a memory request is active, the CS22210 will assert CKE high to cause the SDRAM to come out of power down mode. Typically, this can reduce memory power consumption by up to 50%.
In ROM configuration, firmware for CS22210 is stored in non-volatile memory and is accessed through the Boot ROM interface. The maximum addressable ROM space supported is 1MB. ROM read/write and output enable are shared with RAM control pins. The ROM can be re-flashed allowing for software upgrades.
3.5
PCI Controller Interface
Embedded in the CS22210 is a PCI 2.1 / PCI 2.2 fully compliant master/target 32 bit data interface including power management support (PME signal). The communication buffer logic was designed to be flexible and generic to both the PC software and ARM firmware. The control communication between PCI and ARM uses a mailbox mechanism. The PCI writes data into a Dword mailbox register whereby an interrupt is generated to the ARM. The ARM reads this register to get the control information whereby an interrupt is generated to the PCI. The same is true from the ARM writing to a ARM mailbox register.
PCI data transfer is supported by a DMA Control Block (DCB). The DCB is configured by the ARM, allowing the ARM to control how often it is interrupted. PCI data transfers are done by the PCI master and the DCB offloading CPU overhead.
3.6
USB Interface
Embedded within the CS22210 is a full speed USB 1.1 compliant device interface. The device supports from 1 to 16 endpoints and is completely programmable via firmware download or external EEPROM. All "setup" commands are passed to the system processor for interpretation. The device also contains a DMA engine to transfer arbitrary amounts of data to and from main memory before interrupting the system processor.
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Pinout and Signal Descriptions
Figure 3. CS22210 Logical Pin Groupings (note: not all signals are shown)
nSERR SMCLK nSMCS[1:0] nPERR PCLK AD[31:0] nCBE[3:0] nPERR, nSERR IDSEL nFRAME nIRDY nTRDY nDEVSEL nSTOP NRST NINTA TDO TDI PME nRST nREQ nGNT PARX PCI Controller Interface
System Memory Interface
nSMRAS nSMCAS nSMWE SMDQM[1:0] SMCKE SMA[11:0] SMD[15:0] nBRCE
CS22210 Wireless Network Controller
JTAG Interface
TCK TMS nTRST nRST
SYNTH_LE1 SYNTH_LE2 TXCLK
System and PCI Reset XTALCLKIN Clock Interface XTALOUT XTRACLK PLLAGND PLL Power Interface PLLAVCC PLLDVCC PLLDGND PLLPLUS
TXPE TXD TXRDY CCA BBRNW nRESETBB BBAS nBBCS TXPAPE TXPEBB RXPEBB BBSCLK Digital Wireless Radio
USB_ENUM
BBSDX SYNTHLE nRPD RXCLK MDRDY RXD
USB Interface
USBVPX USBVMX
NTEST DACAVCC & DACAGND
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This section provides detailed information on the CS22210 signals. The signal descriptions are useful for hardware designers who are interfacing the CS22210 with other devices.
System Memory Interface
The system memory interface supports standard SDRAM interface, async SRAM and FLASH. There are total of 37 signals in this interface. SMCLK Output System mem clock for SDRAM. Currently the interface supports 103 MHz for a maximum bandwidth of 200Mbytes/sec. nSMCS0 Output Chip select bit 0. This signal is used to select or deselect the SDRAM for command entry. When SMNCS is low it qualifies the sampling of nSMRAS, nSMCAS and nSMWE. Also used as testmode(2) when NTEST pin is '0'. nSMCS Chip select bit 1. nBRCE Output Chip select for ROM access. This signal is used to select or deselect the boot ROM memory. nSMRAS Output Row address select. Used in combination with nSMCAS, nSMWE and nSMCS to specify which SDRAM page to open for access. Also used during reset to latch in the strap value for clk_bypass; if set to a '1' implies bypassing clock module; whatever clk is applied on the input clock is used for memclk and ctlclk. Also shared as the ROMOE signal. NSMCAS Output Column address select. Used in combination with nSMRAS, nSMWE and nSMCS to specify which piece of data to access in selected page. Also used during reset to latch in the strap value for same_freq; if set to a '1' implies internal mem_clk and arm_clk are running at the same frequency and 180 degrees out of phase. Output
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nSMWE
Output Write enable is used in combination with nSMRAS, nSMCAS, and nSMWE to specify whether the current cycle is a read or a write cycle. Also used during reset to latch in the strap value for tst_bypass; if set to a '1' implies PLL bypass. Also shared as the ROMWE to do flash programming.
SMDQM[1:0]
Output Data mask bit 1:0. These signals function as byte enable lines masking unwanted bytes on memory writes. Also used as testmode(1:0) when NTEST pin is '0'. Output Clock enable. SMCKE is used to enable and disable clocking of internal RAM logic.
SMCKE
SMA0
Output Address bit0. The address bus specifies either the row address or column address. Also shared as boot-rom address bit0. This pin should be pulldown.
SMA1
Output Address bit1. Also shared as boot-rom address bit1. Also used during reset to latch in the strap value for pcisel; if set to a '1' implies pci mode.
SMA2
Output Address bit2. Also shared as boot-rom address bit2. Also used during reset to latch in the strap value for usbsel; if set to a '1' implies usb mode.
SMA3
Output Address bit3. Also shared as boot-rom address bit3. This pin should be pull-down.
SMA4
Output Address bit4. Also shared as boot-rom address bit4. Also used during reset to latch in the strap value for romcfg; if set to a '1' implies pci configuration data should be downloaded from ROM.
SMA5
Output Address bit5. Also shared as boot-rom address bit5. Also used during reset to latch in the strap value for test_rst_enb; if set to a '0' implies normal operation mode.
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SMA6
Output Address bit6. Also shared as boot-rom address bit6. Also used during reset to latch in the strap value for freq_sel(0). Freq_sel(2:0) is used to select the multiplication factor for the internal PLL (000=1x, and 111=8x).
SMA7
Output Address bit7. Also shared as boot-rom address bit7. Also used during reset to latch in the strap value for freq_sel(1). Freq_sel(2:0) is used to select the multiplication factor for the internal PLL (000=1x, and 111=8x).
SMA8
Output Address bit8. Also shared as boot-rom address bit8. Also used during reset to latch in the strap value for freq_sel(2). Freq_sel(2:0) is used to select the multiplication factor for the internal PLL (000=1x, and 111=8x).
SMA9
Output Address bit9. Also shared as boot-rom address bit9. Also used during reset to latch in the strap value for sdram_delay(0). Sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments).
SMA10
Output Address bit10. Also shared as boot-rom address bit10. Also used during reset to latch in the strap value for sdram_delay(1). Sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments).
SMA11
Output Address bit11. Also shared as boot-rom address bit11. Also used during reset to latch in the strap value for sdram_delay(2). Sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments).
SMD[7:0]
Bi-directional Data bus. The data bus contains the data to be written to memory on a write cycle and the read return data on a read cycle.
SMD[15:8]
Bi-directional Shared data bus. The data bus contains the data to be written to RAM memory on a write cycle and the read return data on a read cycle. Data bit [15:8] is also shared as boot ROM address bit [19:12].
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Digital Wireless Radio Interface
All radio input buffers are Schmitt triggered input buffers. There are total of 21 signals in this interface. TXCLK Input Transmit clock is a clock input from the radio baseband processor. This signal is used to clock out the transmit data on the rising edge of TXCLK. TXPEBB Output Baseband transmit power enable, an output from the MAC to the radio baseband processor. When active, the baseband processor transmitter is configured to be operational, otherwise the transmitter is in standby mode. TXD Output It is the serial data output from the MAC to the radio baseband processor. The data is transmitted serially with the LSB first. The data is driven by the MAC on the rising edge of TXCLK and is sampled by the radio baseband processor on the falling edge of TXCLK (in 3824 mode) and rising edge of TXCLK (in 3860B mode). TXRDY Input Transmit data ready is an input to the MAC from the radio baseband processor to indicate that the radio baseband processor is ready to receive the data packet over the TXD signal. The signal is sampled by the MAC on the rising edge of TXCLK. CCA Input Clear channel assessment is an input from the radio baseband processor to signal that the channel is clear to transmit. When this signal is a 0, the channel is clear to transmit. When this signal is a 1, the channel is not clear to transmit. This helps the MAC to determine when to switch from receive to transmit mode. BBRNW Output Baseband read/write is an output from the MAC to indicate the direction of the SD bus when used for reading or writing data. This signal has to be set up to the rising edge of BBSCLK for the baseband processor and is driven on the falling edge of BBSCLK. NRESETBB Output Baseband reset is an output of the MAC to reset the baseband processor.
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BBAS
Output Baseband address strobe is used to envelop the address or the data on the BBSDX bus. Logic 1 envelops the address and a logic 0 envelops the data. This signal has to be set up to the rising edge of BBSCLK for the baseband processor and is driven on the falling edge of BBSCLK.
NBBCS
Output Baseband chip select is an active low output to activate the serial control port. When inactive the SD, BBSCLK, BBAS and BBRNW signals are `don't cares'.
TXPAPE
Output Radio power amplifier power enable is a software-controlled output. This signal is used to gate power to the power amplifier.
TXPE
Output Radio transmit power enable indicates if transmit mode is enabled. When low, this signal indicates receive mode.
RXPEBB
Output Baseband receive power enable is an output that indicates if the MAC is in receive mode. This output to the baseband processor enables receive mode in baseband processor.
BBSCLK
Output Baseband serial clock is a programmable output generated by dividing ARM_CLK by 14 (default). This clock is used for the serial control port to sample the control and data signals.
BBSDX
Bi-directional Baseband serial data is a bi-directional serial data bus, which is used to transfer address and data to/from the internal registers of the baseband processor.
SYNTHLE
Output Synthesizer latch enable is an active high signal used to send data to the synthesizer.
SYNTH_LE1
Output Synthesizer latch enable is an active high signal used to send data to the synthesizer (RF LE).
SYNTH_LE2
Output Synthesizer latch enable is an active high signal used to send data to the synthesizer (IF LE).
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NRPD
Output Radio power down enable is an active low signal used for power management purposes for the radio circuitry.
RXCLK
Input This is an input from baseband processor. It is used to clock in received data from baseband processor.
MDRDY
Input Receive data ready is an input signal from the baseband processor, indicating a data packet is ready to be transferred to the MAC. The signal returns to inactive state when there is no more receiver data or when the link has been interrupted. This signal is sampled on the falling edge of RXCLK (in 3824 mode), and sampled at rising edge of RXCLK (in 3860B mode).
RXD
Input Receive data is an input from the baseband processor transferring demodulated header information and data in a serial format. The data is frame aligned with MD_RDY. This signal is sampled on the falling edge of RXCLK (in 3824 mode), and sampled at rising edge of RXCLK (in 3860B mode).
DACAVCC Analog power for DAC. 3.3V input. DACAGND Analog ground for DAC. RLQ
Input
Input
Output Radio link quality based on packet error rate. Active low implies the packet was received without errors. Note: Lost packets are not detected.
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PLL and Clock Interface
There are three clock pins and five PLL power pins. Total of 8 signals in this interface. XTAL_CLKIN Input 44 MHz reference clock input/crystal clock input for PCI and 48 MHz for USB. XTALOUT Reference crystal clock output. XTRACLK Input Second clock input to clock module. This input allows independent control for mem_clk and ctl_clk. The usage of this clock input is determined by the clk module configuration, which is determined by the three strapping input pin values. PLLAGND Analog PLL ground. PLLAVCC Analog PLL power. 3.3V input. PLLDGND Digital PLL ground. PLLDVCC Digital PLL power. 1.8V input. PLLPLUS Analog PLL ground. Input Input Input Input Input Output
PCI Interface
The PCI interface is a standard 2.2 compliant interface. There are a total of 51 signals. AD[31:0] Bi-directional PCI address/data. This bus contains a physical address during the first clock of a PCI transfer and data during subsequent clocks. The signals are inputs during the address and write data phases of a transaction, or outputs during the read data phase of a transaction.
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nCBE[3:0]
Bi-directional Control/byte enable. This bus defines the bus command during the first clock of a PCI transaction and the data byte enables during subsequent clocks.
IDSEL
I/O OD PCI initialization device select. Used as a chip select during configuration read and write cycles.
nFRAME PCI cycle frame. current bus cycle. NIRDY
Bi-directional This signal marks the beginning and duration of a
Bi-directional PCI initiator ready. IRDY holds off the beginning of a write cycle and the completion of a read cycle until sampled active.
nTRDY
Bi-directional PCI target ready. This signal is driven active to indicate that write data has been sampled or that read data has been delivered.
nDEVSEL
Bi-directional PCI device select. As a medium speed device, this signal is driven active two PCI clocks after NFRAME is sampled active, indicating a positive decode. It remains active until the end of the transaction.
nSTOP
Bi-directional PCI stop. This signal indicates a target initiated termination of the current cycle.
nINTA
Output/Open Drain PCI interrupt request A. Generates an interrupt on the PCI bus.
PCLK
I/O OD PCI clock. Typically a 33 MHz. All CS22210 PCI activity is synchronous to PCLK.
nPERR
Bi-directional PCI parity error. This signal is asserted two clocks after a data parity error is detected on the PCI bus.
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nSERR
Output/Open Drain PCI system error. This open drain signal is used to indicate a fatal parity error on PCI address.
nREQ
Input PCI master request. Used by the PCI master to indicate it needs to drive the PCI bus.
nGNT
Bi-directional PCI master grant. Used by the PCI master to indicate OK to drive the PCI bus.
PAR
Bi-directional PCI parity. This signal is asserted one clock after data transfer has occurred on the PCI bus.
PME
Output/Open Drain Power management event. Use to let the system knows a change in power management event has occurred.
System Reset
nRST Input System reset and PCI reset. Reset is an asynchronous signal that forces the chip to go to a known state. This is an active low signal.
USB Interface
USBVP Bi-directional Differential USB data plus. For high-speed mode, this signal is pull up to 5 volt during IDLE state (see USB_ENUM). . USBVM Differential USB data minus. USB_ENUM Output USB enumeration. Indicates a disconnect/connect event. USB_ENUM is used to pull the D+ line high, indicating to the host or hub a USB bus "full rate" connection is active. Bi-directional
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Debug Interface
TDO Test data output. TDI Test data input. The input has an integral pull up. TCK Test clock signal. TMS Test mode select. The input has an integral pull up. nTRST Test interface reset. The input has an integral pull up. Input Input Input Input Output
Miscellaneous Interface
SPIO 8,9,12,13,16 Bi-directional Special purpose I/O reserved for supporting custom interfaces. * Check with Cirrus Logic support for supported options and usage. nTEST Input Chip test mode pin. Used in conjunction with SMNCS0, SMDQM[0:1]. Pull up for normal operation.
Power and Ground
VCC (5V and 3.3V)
1
Input 5V inputs. There are a total of 3 pins.
VDD (3.3V) 3.3V inputs. There are a total of 26 pins. VEE (1.8V) 1.8 inputs to the core. There are a total of 9 pins. VSS Ground. There are a total of 33 pins.
Input
Input
Input
1
5V or 3.3V depending on desired PCI configuration
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Figure 4. CS22210 208 pin MQFP Pinout Diagram
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Rev. 3.0
Table 1. Pin Listing by pin number pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 name VCC AD29 AD28 AD27 AD26 VDD AD25 VSS AD24 NCBE03 IDSEL VDD AD23 AD22 VSS AD21 AD20 AD19 VDD AD18 AD17 VSS AD16 VEE NCBE02 VSS VEE VSS VCC NFRAME VDD NIRDYX NTRDY VSS NDEVSEL NSTOP NPERR VDD NSERR PAR VSS NCBE01 AD15 AD14 VDD pin 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 name AD13 AD12 VSS AD11 AD10 AD09 VCC VDD AD08 NCBE00 VSS AD07 AD06 AD05 VDD AD04 AD03 VSS AD02 AD01 AD00 SMNCS00 SMNCS01 VDD SMDQM00 SMDQM01 VSS SMNCAS SMCKE SMD00 VDD VSS VEE VEE VSS VDD SMD01 SMD02 VSS SMD03 SMD04 SMD05 SMCLK VSS VDD pin 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 name SMD06 SMD07 SMD08 VSS SMD09 SMD10 SMD11 VDD SMD12 SMD13 SMD14 VSS SMD15 SMA00 SMA01 VSS SMA02 SMA03 SMA04 VDD SMA05 SMA06 SMA07 VSS SMA08 SMA09 VDD SMA10 SMA11 SMNWE VSS SMNRAS NBRCE NTEST VSS VEE VSS VEE BBNCS BBSCLK VDD BBSDX SYNTHLE VSS BBRNW pin 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 name NRESETBB BBAS VDD MDRDY RXD RXCLK VSS RLQ USB_ENUM RXPEBB TXPAPE TXPEBB VDD TXCLK TXRDY TXD VSS TXPE CCA VDD RNPD PLLDVCC PLLDGND PLLAVCC PLLAGND PLLPLUS VDD XTALCLKIN XTALOUT VSS XTRACLK DACAGND RSVD RSVD RSVD RSVD DACAVDD VDD VDD NTRST TMS VSS TDI TDO VDD
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
ball 181 182 183 184 185 186 187
name TCK VSS VEE VSS VEE VEE VSS
ball 188 189 190 191 192 193 194
name VSS USBVP RSVD USBVM RSVD SYNTH_LE1 VDD
ball 195 196 197 198 199 200 201
name RSVD_0 PME VDD NINTA PCLK VSS NGNT
ball 202 203 204 205 206 207 208
name NREQ VDD AD31 NRST AD30 VSS SYNTH_LE2
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
Table 2. Pin Listing by Name pin 66 65 64 62 61 59 58 57 54 51 50 49 47 46 44 43 23 21 20 18 17 16 14 13 9 7 5 4 3 2 206 204 137 129 135 130 132 154 167 172 168 170 11 139 123 name AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 BBAS BBNCS BBRNW BBSCLK BBSDX CCA DACAGND DACAVDD RSVD RSVD IDSEL MDRDY NBRCE pin 55 42 25 10 35 30 201 198 32 37 202 136 205 39 36 124 33 175 40 199 160 159 158 157 161 196 143 156 169 171 190 192 195 141 140 145 104 105 107 108 109 111 112 113 115 name NCBE00 NCBE01 NCBE02 NCBE03 NDEVSEL NFRAME NGNT NINTA NIRDYX NPERR NREQ NRESETBB NRST NSERR NSTOP NTEST NTRDY NTRST PAR PCLK PLLAGND PLLAVCC PLLDGND PLLDVCC PLLPLUS PME RLQ RNPD RSVD RSVD RSVD RSVD RSVD_0 RXCLK RXD RXPEBB SMA00 SMA01 SMA02 SMA03 SMA04 SMA05 SMA06 SMA07 SMA08 pin 116 118 119 74 88 75 82 83 85 86 87 91 92 93 95 96 97 99 100 101 103 70 71 73 67 68 122 120 193 208 133 181 178 179 176 149 151 146 153 147 150 144 191 189 1 name SMA09 SMA10 SMA11 SMCKE SMCLK SMD00 SMD01 SMD02 SMD03 SMD04 SMD05 SMD06 SMD07 SMD08 SMD09 SMD10 SMD11 SMD12 SMD13 SMD14 SMD15 SMDQM00 SMDQM01 SMNCAS SMNCS00 SMNCS01 SMNRAS SMNWE SYNTH_LE1 SYNTH_LE2 SYNTHLE TCK TDI TDO TMS TXCLK TXD TXPAPE TXPE TXPEBB TXRDY USB_ENUM USBVM USBVP VCC pin 29 52 6 12 19 31 38 45 53 60 69 76 81 90 98 110 117 131 138 148 155 162 173 174 180 194 197 203 24 27 78 79 126 128 183 185 186 8 15 22 26 28 34 41 48 name VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VEE VEE VEE VEE VEE VEE VEE VEE VEE VSS VSS VSS VSS VSS VSS VSS VSS
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
ball 56 63 72 77 80 84 89
name VSS VSS VSS VSS VSS VSS VSS
ball 94 102 106 114 121 125 127
name VSS VSS VSS VSS VSS VSS VSS
ball 134 142 152 165 177 182 184
name VSS VSS VSS VSS VSS VSS VSS
ball 187 188 200 207 163 164 166
name VSS VSS VSS VSS XTALCLKIN XTALOUT XTRACLK
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
5
Specifications
Table 3. Absolute Maximum Ratings
Symbol VEE VDD Vin (PCI) VIN IIN XTALIN TSTGP Parameter Voltage at Core DC Supply ( I/O) PCI Voltage Input Voltage DC Input Current Input frequency Storage Temperature Range Limits 1.62 to 2.0 -0.3 to 3.9 -0.5 to 5.25 -0.1 to Vdd + 0.33 +/- 10 0 to 60 -40 to 125 Units V V V V A MHz C
Notes: 1. XTALIN & XTALOUT pins have minimal ESD protection. 2. This device may have ESD sensitivity above 500V HBM per JESD22-A114. Normal ESD precautions need to be followed.
Table 4. Recommended Operating Conditions
Symbol VDD Vcc Vee XTALCLKIN armclk memclk FTCK TA TJ Parameter DC Supply Limits 3.0 to 3.60 (3V I/O) 4.5 to 5.5 (5V I/O) 1.6 to 2.0 (core) 44 or 48 44(4x11) to 77 72 to 103 0 to 10 0 to +70 0 to +105 Units V
Input frequency Internal ARM clock frequency Internal Memory clock frequency JTAG clock frequency Ambient Temperature Junction Temperature
MHz MHz MHz MHz C C
Table 5. Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Value 3.4 4.0 Units pF pF
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
Table 6. DC Characteristics
Symbol VIL VIL VIH VIH VOL VOL VOH VOH IIL IOZ ICC & IDD IEE Parameter Voltage Input Low (PCI) Voltage Input Low (non-PCI) Voltage Input High (PCI) Voltage Input High (non-PCI) Voltage Output Low (PCI) Voltage Output Low (non-PCI) Voltage Output High (PCI) Voltage Output High (non-PCI) Input Leakage Current 3-State Output Leakage Current Dynamic Supply Current Note 1 Condition Min -0.5 -0.33 2.0 0.7 * VDD 0 0.24 Vdd - 0.1 -10 -10 35 135 Typ Max Units 0.8 V 0.3 * VDD V Vcc + 0.5 V VDD + 0.33 V 0.55 V V VSS + 0.1 V Vdd V 10 A 10 A ma
IOL = 1500 A IOL = 800 A IOH = -500 A IOH = 800 A VIN = VSS or VDD VOH = VSS or VDD VCC & DD = 5V & 3.3V VDD = 1.8V
5.1
AC Characteristics and Timing
Table 7. System Memory Interface Timing
Parameter tdSMD tdSMA tdSMDQM tdSMNCS tdSMNWE tdSMCKE tdSMNCAS tdSMNRAS TperSMCLK TsuSMD ThSMD Notes:
1. 2. Outputs are loaded with 35pf on SMD, 25pf on SMA, SMDQM, SMNRAS, and SMNCAS and 20pf on SMCLK, SMNCS, and SMCKE. An attempt has been made to balance the setup time needed by the SDRAM and the setup needed by CS22210 to read data. If there is a problem meeting setup on the SDRAM, there is a programmable delay line on SMCLK which can help meet the setup time. Care must be taken, however, not to violate the setup on the return read data. The delay can be increased by a multiple of 0.25ns by using the SMA[11:09] pins to selectively set the clock delay .
Parameter Description SMCLK to SMD[31:0] output delay SMCLK to SMA[11:0] output delay SMCLK to SMDQM[3:0] output delay SMCLK to SMNCS[1:0] output delay SMCLK to SMNWE output delay SMCLK to SMCKE output delay SMCLK to SMNCAS output delay SMCLK to SMNRAS output delay SMCLK period SMD[31:0] setup to SMCLK SMD[31:0] hold from SMCLK
Min
72 1.0 2.4
Max 7 4.7 5.1 4.1 4.5 4.3 4.0 5.0 103
Units ns ns ns ns ns ns ns ns ns ns ns
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
SMCLK
tdSMD
SMD[15:0]
WRITE DATA tdSMA ROW ADDR COLUMN ADDR tdSMDQM
SMA[13:0]
SMDQM[1:0]
tdSMNCS
SMNCS[1:0]
tdSMNWE
SMNWE
tdSMCKE
SMCKE
tdSMNRAS
SMNRAS
tdSMNCAS
SMNCAS
Figure 5. System Memory Interface `Write' Timing Diagram
tperSMCLK
SMCLK
thSMD tsuSMD
SMD[15:0]
DATA tdSMA
ROW ADDR
SMA[13:0] SMDQM[1:0]
COLUMN ADDR
tdSMNCS
SMNCS[1:0] SMNWE
ACTIVE tdSMCKE
SMCKE
tdSMNRAS
SMNRAS
tdSMNCAS
SMNCAS
Figure 6. System Memory Interface 'Read' Timing Diagram
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
Table 8. ROM/Flash Memory Read Timing
Item
Clock Period (1)
Symbol tperSMCLK tid SMD tf SMRAS tACC td SMA td BRCE td SMRAS tsu SMD th SMD 1.0 ns 2.4 ns Min 72 MHz 6(tperSMCLK) 220 ns 4.0 ns 4.5 ns 5.0 ns Max 103 MHz 221 ns
CE to SMD Latched Data (2) OE de-asserted to OE asserted (3) ROM address to output delay (4) SMCLK to SMA output delay SMCLK to BRCE output delay (CE) SMCLK to SMRAS output delay (OE) SMD setup to SMCLK SMD hold from SMCLK Notes:
1. The memclock timing is derived by bootstrap PLL settings. Synchronous modes at 77 MHz & 72 MHz are currently supported. 2. tid SMD is based on the fm_romrdlat register settings - default is 09h max. (77Mhz ~ 17 times SMCLK = 221ns). 3. tf SMRAS is the minimum time required before the next OE is active on the bus (6 times SMCLK). The ROM device must release the bus within this time frame (77MHz ~ 78 ns). 4. Based on default fm_romrdlat register settings (note: 09h translates to 11h) see fm_romrdlat register settings for more
information).
SMCLK tper SMCLK
t ld
SMD
tf
SMRAS
t ACC
SMD[7:0]
tsu
SMD
th
SMD
DATA td
SMA
SMA[11:0], SMD[13:8]
ADDRESS
SMNWE
td
BRCE (CE)
BRCE
td
SMRAS
BRCE
td
SMRAS (OE)
td
SMRAS
Figure 7. ROM Memory Interface 'Read' Timing Diagram
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
Table 9. PCI Interface Timings
Parameter tdAD tdNCBE tdNFRAMEX tdNDEVSELX tdNIRDYX tdNTRDYX tdNSTOPX tdPARX tdNPERRX tdNSERR TsuALL ThALL Parameter Description PCLK to ADX[31:0] output delay PCLK to NCBEX[3:0] output delay PCLK to NFRAMEX output delay PCLK to NDEVSELX output delay PCLK to NIRDYX output delay PCLK to NTRDYX output delay PCLK to NSTOPX output delay PCLK to NPARX output delay PCLK to NPERRX output delay PCLK to NSERR output delay All inputs setup to PCLK All inputs hold from PCLK Min Max 10.93 10.93 10.93 10.92 10.92 10.92 10.92 10.92 10.93 10.93 Units ns ns ns ns ns ns ns ns ns ns ns ns
5 1.1
Notes: All outputs are loaded with 50pf.
Table 10. USB Interface Timings
Parameter USBVPX USBVPM Description Differential data positive Differential data negative Min 4 4 Max 20 20 Units ns ns
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
Table 11. Radio MAC AC Timings - Intersil Modes
Parameter tdBBAS tdBBRNW tdnBBCS tdBBSDX TsuBBSDX ThBBSDX tdTXD tdTXD TsuRXD ThRXD TsuMDRDY ThMDRDY tdTXPEBB tdRXPEBB TsuTXRDY ThTXRDY TdutyRXCLK 2 TdutyTXCLK 2 Parameter Description BBAS output delay from falling BBSCLK BBRNW output delay from falling BBSCLK nBBCS output delay from falling BBSCLK BBSDX output delay from falling BBSCLK BBSDX setup to rising edge of BBSCLK BBSDX hold from rising edge of BBSCLK TXD output delay from rising TXCLK (SMAC Mode) TXD output delay from rising TXCLK (RMAC Mode) RXD setup to rising edge of RXCLK RXD hold from rising edge of RXCLK MDRDY setup to falling edge of RXCLK MDRDY hold from falling edge of RXCLK TXPEBB output delay from rising TXCLK RXPEBB output delay from rising RXCLK TXRDY setup to falling edge of TXCLK TXRDY hold from falling edge of TXCLK RXCLK period TXCLK period Min Max 8.2 8.0 59.0 7.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
14.8 0.0 33.5 15.4 1.0 1.8 2 1 15.0 16.0 6.5 0 See Note See Note
Notes: 1. CCA signal is double synchronized to ARMCLKIN. 2. ARMCLK must be at least 4 times the TXCLK and RXCLK frequency. 3. Harris baseband (3824/3824A) generates RXCLK and TXCLK of 4 Mhz. the duty cycle varies between 33-40% with a high time of 90.9ns and low time that alternates between 136 and 182ns. The clock period varies between 227 and 272 ns, giving an effective period of 250ns. 4. TXD delay in 802.11b mode is the result of sampling the TXCLK with the ctlclk, therefore the maximum delay is equal to two ctlclk periods plus the flop-to-output delay. In this table, ctlclk is assumed to have a 13 ns period. 5. BBNCS output delay = [(1/ARMCLK freq)*ceiling(SER_CLK_DIV/2)] + 7ns, the specified value is based on ARMCLK of 77 Mhz and SER_CLK_DIV=8.
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
Table 12. Radio MAC AC Timings - RFMD Modes
Parameter tdBBRNW tdnBBCS tdBBSDX TsuBBSDX ThBBSDX tdTXD tdTXD TsuRXD ThRXD TsuMDRDY ThMDRDY tdTXPEBB tdRXPEBB TsuTXRDY ThTXRDY Notes:
1. 2. 3. Signal is double synchronized to ARMCLKIN. ARMCLK must be at least 4 times the TXCLK and RXCLK frequency. TXD delay in 802.11b mode is the result of sampling the TXCLK with the ctlclk, therefore the maximum delay is equal to two ctlclk periods plus the flop-to-output delay. In this table, ctlclk is assumed to have a 13 ns period. BBNCS output delay = [(1/ARMCLK freq)*ceiling(SER_CLK_DIV/2)] + 7ns, the specified value is based on ARMCLK of 77 Mhz and SER_CLK_DIV=8.
Parameter Description BBRNW output delay from falling BBSCLK nBBCS output delay from falling BBSCLK BBSDX output delay from falling BBSCLK BBSDX setup to rising edge of BBSCLK BBSDX hold from rising edge of BBSCLK TXD output delay from rising TXCLK (SMAC Mode) TXD output delay from rising TXCLK (RMAC Mode) RXD setup to rising edge of RXCLK RXD hold from rising edge of RXCLK MDRDY setup to falling edge of RXCLK MDRDY hold from falling edge of RXCLK TXPEBB output delay from rising TXCLK RXPEBB output delay from rising RXCLK TXRDY setup to falling edge of TXCLK TXRDY hold from falling edge of TXCLK
Min
Max 6.7 110.79 7.0
14.5 0.0 33.5 15.4 1.0 1.8 2 1 15.0 16.0 6.5 0
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4.
5.2
Table 13. Package Specifications
Symbol JC JA PMAX TJ_MAX
Parameter Junction-to-Case Thermal Resistance Junction-to-Open Air Thermal Resistance Max Power Dissipation Max Junction Temperature
Value 5 29.4 1.0 105
Units C/W C/W W C
Notes: 1. ARMCLK / MEMCLK = 77MHz
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0
6
Packaging
The CS22210 controller is available in a 208 MQFP package. Figure 8 contains the package mechanical drawing. Figure 8. CS22210 208 MQFP-pin Mechanical Drawing
CS22210 PCI/USB Wireless Controller
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D556PP2
Rev. 3.0

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